1. Field of the Invention
Our invention relates to testing, including pattern generation and address testing of integrated circuits, and more particularly, microprocessor chips containing multi-port arrays. A further aspect of the invention is the testing relationship between the read and write address ports.
2. Description of Background
Array macros are used in microprocessors to store information. Hardware errors affect these arrays in array cells, wordlines, bitlines, etc. ABIST (Array Built-In Self Test) engines are used to test for these errors and to help diagnose the root cause of any problem. ABIST engines are described in U.S. Pat. No. 5,954,830, Method And Apparatus For Achieving Higher Performance Data Compression In ABIST Testing By Reducing The Number Of Data Outputs; and U.S. Pat. No. 5,442,641 Fast Data Compression Circuit For Semiconductor Memory Chips Including An Array Built-In Self-Test Structure.
One type of an array is the multi-port array. Cells that each contain separate read and write ports as opposed to the standard single port 6-device cell characterize multi-port arrays. With a multi-port array the user is able to read and write data to different cells on the same cycle. However, if the user asks for a read operation and a write operation at the same address, the write is guaranteed, but the read is not. The testing for multi-port array macros is more complex than testing for the standard single port arrays.
One problem with ABIST engines as applied to multi-port arrays is that separate address counters are needed for the read and write ports. The result is that the separate address counters for the read and write ports increase the ABIST logic that is needed. This leads to increased ABIST size. One solution is use the same address counter for the read and write addresses, except that one bit is inverted to avoid reading and writing the same address in one cycle. Unfortunately, this artifact does not provide much flexibility in testing. Thus, a clear need exists for a more refined method for controlling the relationship between the read and write addresses would improve testing capability for multi-port arrays.